This invention relates to semiconductor memory devices, and more particularly to N-channel silicon gate MOS read only memories and methods for programming.
Storage of fixed programs in digital equipment such as microcomputers and microprocessor systems is usually provided by MOS read only memory devices or "ROMs". ROMs are made by semiconductor manufacturers on special order, the programming code being specified by the customer. The economics of manufacture of ROMs, and of mounting them on circuit boards in the system, are such that the number of memory bits per semiconductor chip is advantageously as high as possible. ROMs of up to 32K bits (32768) are typical at present. Within a few years, standard sizes will progress through 64K, 128K and 1 megabit. This dictates that cell size for the storage cells of the ROM be quite small. Metal gate ROMs of small size can be relatively easily fabricated in the manner set forth in U.S. Pat. Nos. 3,541,543, and 4,061,506, assigned to Texas Instruments. Most microprocessor and computer parts are now made by the N-channel silicon gate process because of the shorter access times provided. In the past, ROMs made by the N-channel process have been programmed by the moat mask or by contacts between output metal lines and N+ drain regions. N-channel ROMs are disclosed in prior applications Ser. No. 762,612, now U.S. Pat. No. 4,151,020, filed Jan. 29, 1977 and Ser. No. 701,932 now abandoned, filed July 1, 1976 and Ser. No. 907,235, filed May 18, 1978 assigned to Texas Instruments. A method of programming a ROM by ion implant prior to forming the polysilicon gate is shown in U.S. Pat. No. 4,059,826 to Gerald D. Rogers, assigned to Texas Instruments. Methods of programming N-channel ROMs by implant through polysilicon gates are shown in copending applications Ser. Nos. 890,555, 890,556, and 890,557, filed Mar. 20, 1978, and 907,236, filed May 18, 1978, assigned to Texas Instruments. These methods required that no metal overlie the gates so "SATO" type processing was used so that no metal was in the ROM array, or otherwise used processing different from the standard "NSAG" which is in large volume use.
In these and other prior methods of programming, capacitance between the X address lines and the output, substrate or ground, or between the output lines and the substrate or ground, was not minimized. Such capacitance adds to delays in the access time or cycle time. When cells are programmed "zero", i.e., the potential transistors not programmed in, needless capacitance is nevertheless introduced. In very large arrays with 256, 512 or 1024 cells on a single line, the capacitance can be very detrimental.
It is the principal object of this invention to provide a semi-conductor permanent store memory programmed in a manner which reduces unwanted capacitance, yet still uses the standard high volume N-channel process. Another object is to provide a semiconductor ROM which is made by the standard N-channel self-aligned silicon gate manufacturing process and is programmable to remove the capacitance of cells which contain "unrealized" transistors.